This invention relates to semiconductor memory devices, and in particular, the present invention relates to semiconductor random access memory devices that utilize a magnetic field.
Memory devices are an extremely important component in electronic systems. The three most important commercial high-density memory technologies are SRAM (static random access memory), DRAM (dynamic random access memory), and FLASH (a form of non-volatile random access memory). Each of these memory devices uses an electronic charge to store information and each has its own advantages. SRAM has fast read and write speeds, but it is volatile and requires large cell area. DRAM has high density, but it is also volatile and requires a refresh of the storage capacitor every few milliseconds. This requirement increases the complexity of the control electronics.
FLASH is the major nonvolatile memory device in use today. Typical non-volatile memory devices use charges trapped in a floating oxide layer to store information. Drawbacks to FLASH include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 104-106 cycles before memory failure. In addition, to maintain reasonable data retention, the thickness of the gate oxide has to stay above the threshold that allows electron tunneling, thus restricting FLASH""s scaling trends.
To overcome these shortcomings, new magnetic memory devices are being evaluated. One such device is magnetoresistive RAM (hereinafter referred to as xe2x80x9cMRAMxe2x80x9d). MRAM has the potential to have speed performance similar to DRAM. To be commercially viable, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds. Conventional MRAM devices store information by programming a free magnetic layer of a bit storage cell to have its magnetic moment either parallel or anti-parallel to that of a fixed magnetic layer. The two magnetic layers are located on either side of a thin insulating barrier forming a magnetoresistive tunnel junction. The electrical resistance of this tunnel junction is either low (parallel) or high (anti-parallel) depending on the relative orientation of the magnetic moments. To readout the MRAM state, the resistance of a bit cell is compared to that of a reference cell. The reference cell is usually another MRAM bit or group of bits that is magnetically set at the time of fabrication and not switched during operation of the MRAM. These bits may be combined to form a midpoint reference for comparison. All bits in the low state will have a resistance lower than these midpoint reference bits, therefore providing the means to determine the state of the bit.
The main problem with this approach is that there can be significant bit-to-bit resistance variations due to variations in material and process quality. These variations may at times make it impossible to distinguish and isolate the high, low and midpoint resistances from one another. For example, if a low resistance bit is in the tail of the distribution significantly above the mean, it may overlap with the tail of the midpoint cell distribution and be impossible to determine or be determined incorrectly. Depending on the amount of resistance variation, a large array could have many bits in the overlap regions.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.